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Methodology
Level 1 : Research on 3rd generation chiplet integrated circuit design methodology and SI/PI analysis techniques following the chiplet standard interfaces
Level 2 : Research on chiplet-integrated circuit layout design by building the standard chiplet design/verification flow and developing optimized methodology of heat, power consumption and SI/PI
Level 1
Level 2
Research on chiplet floor-planning methodology by optimizing transmission/reception latency and voltage drop of 3rd generation chiplet integrated circuit to follow the chiplet standard interfaces
Research on chiplet floor-planning methodology through chiplet modeling for SI/PI integrated analysis and heat/power consumption analysis of 3rd generation chiplet integrated circuit
Building hardware design and verification flow for 3rd generation chiplet integrated circuits
Building a standardized framework for 3rd generation chiplet integrated design
Research on SI/PI analysis techniques for 3rd generation chiplet integrated circuits
Research on SI/PI verification and optimized methodology for 3rd generation chiplet integrated circuits