RESEARCH
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Architecture
Level 1
Designing configurable CIN structures including shared cache, supporting system-level performance evaluation
Design Test & Repair logic for CIN
Level 2
Expanding shared cache structures to 3D stacked logic
RTL generation including CIN automatic optimization and Test & Repair logic
Level 1
Level 2
Designing configurable CIN structures supporting system-level performance evaluation
Development of auto-optimizing methodology and RTL generator for CIN structure, considering chiplet platform configuration
Research on shared cache structures with efficient multi-chiplet data access handling
Research on 3D vertical stacking of shared cache and automatic architecture modeling
Designing 3rd generation chiplet Test & Repair circuit for high reliability and high yield
Research on automatic generation technology for 3rd generation chiplet Test & Repair circuit for high reliability and high yield